Traditionally, memories such as dynamic random access memories (DRAMs) have been designed to operate strictly in accordance with commands from memory controllers such that known DRAM devices execute received commands in a passive manner without deviation. Thus, DRAM devices have traditionally had little to no independent logic and, thus, have exhibited a low-degree of autonomy. For example, synchronous DRAM (SDRAM) devices operate in accordance with a clock signal such that communications (e.g., read, write, data communications) must be received, processed, and output in accordance with strict timing guidelines associated with the clock signal.
Traditional DRAM physical interfaces include separate address and data lines and separate command lines to accommodate communications between a memory controller and memory devices. To perform read or write operations, a memory controller first sends part of an address called a row address, which a DRAM uses to identify a bank and read a corresponding row. The memory controller then sends a column address to identify a particular cache line in an open row. In addition, the memory controller sends separate control signals to differentiate between row addresses and column addresses. Thus, a DRAM relies on numerous signals and communications from a memory controller for a significant amount of its operations.